1. Field of the Invention
The present invention relates to a semiconductor storage device, and more specifically, to a DRAM (Dynamic Random Access Memory)
2. Description of Related Art
A DRAM cell storing data with a capacitative element has been known as a semiconductor storage device. In the DRAM, the data is read out or written after executing a precharge operation, which is an operation of setting bit lines to a predetermined level. A half VDD precharge method has been typically executed in which the bit lines are set to the level around the midpoint potential between a power supply potential VDD and a ground potential GND as the precharge level. However, as the power supply voltage VDD decreases, the level set in the precharge operation has also been decreasing. Therefore, according to the related half VDD precharge method, the precharge level and a threshold value of a sense amplifier are quite close to each other, which makes it impossible to execute the sense operation with accuracy. In order to overcome this problem, a technique of applying the ground potential (GND) level to the precharge level has been employed in recent years. A technique of precharging the level of the bit lines to GND is disclosed in Japanese Unexamined Patent Application Publication No. 2004-265533.
FIG. 7 shows a circuit structure with one bit line pair of a DRAM cell executing a GND precharqe according to a related art. In the circuit shown in FIG. 7, memory cells CELLT (hereinafter referred to as main cell) holding actual data and reference cells (hereinafter referred to as Ref cell) CELLRef outputting reference voltage are connected to each of bit line pair BT and BN. A precharge circuit PRE and a sense amplifier SA are also connected between the bit line pair.
Now, an operation of reading out the main cell connected to the bit line BT of the related circuit will be described. Before starting the reading operation, the bit line pair BT and BN is precharged to a ground potential. When word lines WL and WRN are raised, the memory cell CELLT and the Ref cell CELLRef release the charge held therein to the bit lines BT and BN. At this time, the Ref cell CELLRef outputs substantially half the voltage of the voltage corresponding to “H” level output from the main cell CELLT. Accordingly, even when “L” level is held in the main cell CELLT, the sense amplifier SA can execute the normal sense operation.
Then the sense amplifier SA is operated by a sense amplifier activating signal SE. The sense amplifier SA amplifies a voltage difference of the bit line pair, and a normal operation such as reading is performed. Upon completion of the operation such as the reading, the bit line pair is again precharged to GND. This operation is executed by the precharge circuit RRE which is activated by the rise of the precharge signal PDL. A word line WRPN is raised in the precharge operation. A transistor TRVRef formed in the Ref cell connects the Ref cell CELLRef to a reference voltage source which is the different from the power supply for the bit line and outputs substantially half the voltage (1/2 VDD) of the power supply voltage.
Due to this operation, when the Ref cell holds the charge outputting the “H” level, and the bit line BN is in the “H” level in the reading operation by the operation of the sense amplifier SA, substantially half the charge is discharged from the Ref cell. Substantially half the voltage of the voltage corresponding to the “H” level from the main cell in the reading operation is output by the operation of connecting the Ref cell to 1/2 VDD in the precharge operation.
According to the above operation, the Ref cell needs to be charged or discharged to 1/2 VDD by the reference voltage source outputting 1/2 VDD while precharging the bit lines to GND. Although only one main cell and one Ref cell are connected to one word line in FIG. 7, several hundreds or several thousands of main cells and Ref cells are actually connected to one word line. Therefore, if there is a need to charge all the Ref cells connected to one word line by the reference voltage source outputting 1/2VDD, the ability of the reference voltage source as the power supply circuit needs to be made sufficiently high in order to charge all the Ref cells to 1/2 VDD within the precharge period On the contrary, if all the Ref cells are to be discharged, it may be sometimes impossible to perform discharge for the sufficient amount in the precharge period, and the voltage of the Ref cell may not be decreased to 1/2 VDD.
When the ability of the power supply circuit of the reference voltage source is made high, the power supply circuit itself can be larger. Even when the voltage of the Ref cell is stabilized by an element such as a stabilizing capacitor, the circuit size can be larger due to the increase of the number of elements.